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JTAG - How to instantiate the BSCAN symbol to use JTAG in xc4000 and Spartan devices using HDL?
Record #6676
Problem Title:
JTAG - How to instantiate the BSCAN symbol to use JTAG in xc4000 and Spartan devices using
HDL?
Problem Description:
Urgency: Standard
General Description:
Using VHDL to access the JTAG capabilities of the xc4000 family.
Solution 1:
-- VHDL example to instantiate the BSCAN Macro
-- in Xilinx Devices. This code should be used
-- only for reference
entity example is
port (a, b: in bit; c: out bit);
end example;
architecture xilinx of example is
component bscan
port(tdi, tms, tck: in bit; tdo: out bit);
end component;
component TCK
port ( I : out bit );
end component;
component TDI
port ( I : out bit );
end component;
component TMS
port ( I : out bit );
end component;
component TDO
port ( O : in bit );
end component;
signal tck_net : bit;
signal tdi_net : bit;
signal tms_net : bit;
signal tdo_net : bit;
begin
u1: bscan port map (tdi=>tdi_net, tms=>tms_net, tck=>tck_net, tdo=>tdo_net);
u2: tck port map (i=>tck_net);
u3: tdi port map (i=>tdi_net);
u4: tms port map (i=>tms_net);
u5: tdo port map (o=>tdo_net);
process(b)
begin
if (b'event and b='1') then
c <= a;
end if;
end process;
end xilinx;
End of Record #6676 - Last Modified: 01/10/00 19:44 |
