Answers Database
LogiCORE PCI 64/66 Virtex: VHDL- 2040 Warnings about unsupported attributes (syn_edif_bit_format, syn_edif_scalar_format, black_box)
Record #6691
Product Family: Software
Product Line: LogiCore
Product Part: PCI Core Generator
Product Version: 3.0
Problem Title:
LogiCORE PCI 64/66 Virtex: VHDL- 2040 Warnings about unsupported attributes
(syn_edif_bit_format, syn_edif_scalar_format, black_box)
Problem Description:
Urgency: Standard
General Description: When analyzing the pci files for the 64/66 Virtex core, numerous warnings
appear in the console regarding unsupported attributes: (shown here in FPGA Express)
Warning: Attribute syn_edif_bit_format not supported for synthesis on line 117 (VHDL-2040)
Warning: Attribute syn_edif_scalar_format not supported for synthesis on line 118 (VHDL-2040)
Warning: Attribute syn_edif_bit_format not supported for synthesis on line 783 (VHDL-2040)
Warning: Attribute syn_edif_scalar_format not supported for synthesis on line 784 (VHDL-2040)
Warning: Attribute black_box not supported for synthesis on line 785 (VHDL-2040)
Warning: Attribute syn_noclockbuf not supported for synthesis on line 104 (VHDL-2040)
Warning: Attribute syn_edif_bit_format not supported for synthesis on line 105 (VHDL-2040)
Warning: Attribute syn_edif_scalar_format not supported for synthesis on line 106 (VHDL-2040)
Warning: Attribute syn_edif_bit_format not supported for synthesis on line 51 (VHDL-2040)
Warning: Attribute syn_edif_scalar_format not supported for synthesis on line 52 (VHDL-2040)
Solution 1:
In the newest versions of the PCI core, all the flows stem from the same source files. Where before
there was a directory for Express, FC, etc., now there is only one for VHDL and one for Verilog. Th
e
attributes in question are for the Synplicity flow, and will produce warnings both in FC and FPGA
Express. They can be safely ignored.
End of Record #6691 - Last Modified: 06/04/99 13:41 |
