Answers Database 1999 Databook: Dual-Port RAM table for XC4000E CLB Edge-Triggered (Synchronous) RAM Switching Characteristic Guidelines. Record #6705 Problem Title: 1999 Databook: Dual-Port RAM table for XC4000E CLB Edge-Triggered (Synchronous) RAM Switching Characteristic Guidelines. Problem Description: Urgency: standard General Description: 1999 Databook (page 6-102) and latest datasheet on the web (page 6-108) has error in following section: XC4000E CLB Edge-Triggered (Synchronous) RAM Switching Characteristic Guidelines. Dual-Port RAM table for -4 min, values. Address write cycle time (clock K period) 15.0 Clock K pulse width (active edge) 7.5 Address setup time before clock K 7.5 Address hold time after clock K 2.8 DIN setup time before clock K 0 DIN hold time after clock K 2.2 WE setup time before clock K 0 WE hold time after clock K 2.2 Data valid after clock K 0.3 (The data has been erroneously shifted by one row starting from 7.5) Solution 1: Solution: The correct values should be: Address write cycle time (clock K period) 15.0 Clock K pulse width (active edge) 7.5 Address setup time before clock K 2.8 Address hold time after clock K 0 DIN setup time before clock K 2.2 DIN hold time after clock K 0 WE setup time before clock K 2.2 WE hold time after clock K 0.3 Data valid after clock K (left blank as we do not guarantee min value ) End of Record #6705 - Last Modified: 09/14/99 07:20

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