Answers Database
2.1i Virtex Map - ERROR:xvkpu - Unable to obey design constraints...
Record #6708
Product Family: Software
Product Line: FPGA Implementation
Product Part: map
Product Version: 2.1i
Problem Title:
2.1i Virtex Map - ERROR:xvkpu - Unable to obey design constraints...
Problem Description:
An apparently legal slice configuration is rejected by map which fails with the message:
ERROR:xvkpu - Unable to obey design constraints (MACRONAME = hset, RLOC =
R3C0.S1) which require the combination of the following symbols into a single slice:
RAM symbol "$I50" (Output Signal = I0)
MUXCY symbol "$I35" (Output Signal = $I35/O)
MUXCY symbol "$I36" (Output Signal = $I36/O)
RAM symbol "$I49" (Output Signal = I1)
There is a conflict for the F function generator position.
For this case, the failure is due to a bug related to constant pushing. Many of the input
pins are being driven by GND.
Solution 1:
This problem is fixed in the latest 2.1i Service Pack available at:
http://support.xilinx.com/support/techsup/sw_updates/
Solution 2:
For this case, the failure is due to a bug related to constant pushing. Many of the input
pins are being driven by GND. A work around is to buffer the GND signals driving input
pins to the slice and place a KEEP property on the output net of the buffer.
End of Record #6708 - Last Modified: 10/18/99 10:09 |
