Answers Database
FPGA Configuration: Done goes not high, STARTUP block used
Record #6709
Problem Title:
FPGA Configuration: Done goes not high, STARTUP block used
Problem Description:
Urgency: Standard
General Description:
Device seems to complete configuration, but startup sequence is not completed.
Done goes not high.
Solution 1:
One possible problem can occur when the customer uses the startup primitive.
When the customer connects the clk pin of the startup primitive to ground, bitgen sees, that the Sta
rtup clk is used (it doesn't realize that it is a ground) and uses the ground as clock for startup.
This is why the done pin never goes high.
Regenerate the bit stream with the '-g StartupClk:CCLK' option in bitgen.
For more details see solution #4681:
(Xilinx Solution 4681)
Solution 2:
It is possible that this is a synthesis (Synopsys) problem.
When the user instantiates the startup block but does not connect the clk pin, Synopsys sees, that t
he input is not used and grounds the clock pin. Bitgen sees, that the Startup clk is used (it doesn
't realize that it is a ground) and uses the ground for startup. This is why the done pin never goe
s high.
Regenerate the bit stream with the '-g StartupClk:CCLK' option in bitgen.
For more details see solution #4681:
(Xilinx Solution 4681)
End of Record #6709 - Last Modified: 10/12/99 16:45 |
