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A1.5/F1.5 RAM16X1D Dual port RAM: Doing a read on the dpra port reads an 'X' when the clock not defined, even though this is an async read RAM
Record #6718
Problem Title:
A1.5/F1.5 RAM16X1D Dual port RAM: Doing a read on the dpra port reads an 'X' when the clock
not defined, even though this is an async read RAM
Problem Description:
Urgency: Standard
General Description:
I am using the RAM16X1D, and in simulation I am seeing X when doing a read
on the dpra port. I have the write address (a3 to a0) at a known value, the
write enable is low, but I the clock is undefined.
Shouldn't I be able to do a read on the dpra port even though the clock is
undefined?
Solution 1:
This is a VHDL simulation model problem that is will be fixedd in the
next release of the Xilinx software.
Currently during simulation if a read operation is to be performed then
the user must ensure that all inputs are at a known level.
This is fixed in 2.1i
End of Record #6718 - Last Modified: 06/26/99 08:34 |
