Answers Database
LogiCORE PCI32 Virtex: VHDL version of the core requires more slices than the Verilog version
Record #6759
Product Family: Documentation
Product Line: PCI Apps
Product Part: PCI Frequently Asked Questions
Problem Title:
LogiCORE PCI32 Virtex: VHDL version of the core requires more slices than the Verilog
version
Problem Description:
Urgency: Standard
General Description:
Running the PING design with the VHDL version of the core
requires 949 slices while running the Verilog version requires only
371 slices. Why does the Verilog flow use less number of slices
as compared to the VHDL version?
Solution 1:
Both versions of the PING design are supposed to have two
BARs enabled. The problem is that one extra BAR was
enabled in VHDL. The VHDL design will simulate/work
correctly, as it is a superset of the correct design -- but the
CLB/Slice usage would be higher.
This will be fixed in the next release. In the mean, Users can
disable the additional BAR in the VHDL flow by modifying
the cfg_ping.VHD file as documented in the USER guide.
End of Record #6759 - Last Modified: 08/02/99 15:29 |
