Answers Database
V1.5 COREGEN, VIRTEX, BLOCK RAM: Block RAM generated EDIF still contains <> bus delimiters when ( ) (parentheses) or [ ] (square brackets) were specified as the desired delimiter
Record #6886
Product Family: Software
Product Line: LogiCore
Product Part: Coregen IP Modules
Problem Title:
V1.5 COREGEN, VIRTEX, BLOCK RAM: Block RAM generated EDIF still contains <> bus delimiters
when ( ) (parentheses) or [ ] (square brackets) were specified as the desired delimiter
Problem Description:
Urgency: standard
General Description:
The CORE Generator Block RAM EDIF still has <> bus delimiters in it
when ( ) (parentheses) or [ ] (square brackets) are specified
Solution 1:
There will still be angle bracket ("< >" ) bus delimiters in the EDIF
netlist associated with Xilinx primitives even when you specify a
different bus delimiter format. These angle bracketed bus delimiters
will be associated with lower level Xilinx components that are used
to build the RAM.
The only bus delimiters that will change when you specify a different
bus delimiter format are those that are associated with the interface ports
of the RAM that must interface with the EDIF produced by the third party s
ynthesis tool.
End of Record #6886 - Last Modified: 06/30/99 07:54 |
