Answers Database LogiCORE PCI: Known issues with 2.1 functional simulation for the Spartan, Spartan-XL and 4KXLA PCI cores Record #6912 Product Family: Documentation Product Line: LogiCore Product Part: PCI Protocol Checklist Product Version: 1.0 Problem Title: LogiCORE PCI: Known issues with 2.1 functional simulation for the Spartan, Spartan-XL and 4KXLA PCI cores Problem Description: Urgency: Standard General Description: Known issues with functional simulation while using the PCI LogiCOREs for Spartan-XL, Spartan and 4KXLA devices with the 2.1i software Solution 1: 1. The verilog functional simulation requires a new M2.1i compiled PCI core simulation model, otherwise, IO declaration mismatch occurs in unisims components OBUFT etc. 2. Simulation model "glbl.v" needs to be compiled along with other       PCI design files as unisim models (IBUF etc) refer to glbl.GTS. 3. /verilog/data directory is not required in compile script. Instead,       path for simprims has changed to /verilog/src/simprims. 4. There is a common unisims directory now instead of UNISPARTANXL,       UNI4000X, UNIVIRTEX etc. 5. For compliance testbench simulation, the simulation models for       FK_ARB, FK_TRG and FK_APP should have correct IO declaration       (.I Vs .IN, .O Vs .OUT) while "glbl" should not be instantiated in       testbnch.v 6. VHDL function simulation has no issues and works same as M1.5i End of Record #6912 - Last Modified: 06/29/99 13:11

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