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1.5isp2 xvkdr:42 signal clock (clk2x) is driving pin in of u4 (bufg)
Record #6947
Problem Title:
1.5isp2 xvkdr:42 signal clock (clk2x) is driving pin in of u4 (bufg)
Problem Description:
Urgency: Standard
When doing offchip synchronization using the CLKDLL multiple outputs can be used in the circuit. Ap
p Note 132 shows an example in Figure 11.
Solution 1:
If multiple outputs from this clkdll need to be used multiple CLKDLL need to be instantiated as seen
in the app note. Another output can be used though on the second clkdll.
End of Record #6947 - Last Modified: 07/06/99 12:02 | 
