Answers Database
2.1i: TRCE/NGDBUILD/Timing Analyzer/FPGA Editor: MIN delays & changing speed grades after implementation does not work
Record #6959
Product Family: Software
Product Line: Merged Core
Product Part: Timing
Problem Title:
2.1i: TRCE/NGDBUILD/Timing Analyzer/FPGA Editor: MIN delays & changing speed grades after
implementation does not work
Problem Description:
Urgency: Standard
General Description:
When running the '-min' switch for NGDBUILD/TRCE
or 'min values' for Timing Analyzer, the speed grade
does not change and the timing values don't change
in the timing reports.
&
After changing the speed grade when running TRCE or
Timing Analyzer on an NCD file from PAR, the timing
reports reflect the originally implemented speed grade
and the corresponding timing value. The new speed
grade and timing values are not displayed.
Solution 1:
This issue has been resolved in a Service Pack for 2.1i:
http://support.xilinx.com/support/techsup/sw_updates
End of Record #6959 - Last Modified: 10/15/99 15:22 |
