Answers Database
2.1i Virtex PAR - PAR is failing to allow 2 DLL design with 3 BUFGs to complete.
Record #6984
Product Family: Software
Product Line: FPGA Implementation
Product Part: par
Product Version: 2.1i
Problem Title:
2.1i Virtex PAR - PAR is failing to allow 2 DLL design with 3 BUFGs to complete.
Problem Description:
PAR is generating an ERROR for a valid design with 2 CKLDLLs cascaded together
through a BUFG and feeding a total of 3 BUFGs. The first CLKDLL feeds a single
BUFG and the second DLL feeds two BUFGs.
ERROR:Place:1631 - Could not find a legal placement for the f
ollowing components:
Clk30
DLL0
BFG0
DLL1
BFG1
BFG2
ERROR:Place:1632 - Xilinx requires that such connected GCLK/GCLKIO/DLL
components be placed on the same chip edge. Current design constraints do not
allow this.
The above connectivity is allowed and a valid placement can be found, even with all
of the cells LOC'ed to the correct places in the UCF file the design still fails to complete.
Solution 1:
Solution:
These new error messages are for checking the validility of the IBUFG, CLKDLL
and BUFG placement. The M1.5i tools did not check on the placement and allowed
some unstable placements to exist. These new checks have the following rules:
1) IBUFGs must be on the same edge as the CLKDLL that they drive.
2) BUFGs must be on the same edge as the source CLKDLL.
Violating these rules will generate a bad CLKDLL circuit.
There is however an problem that was missed in the new check that will generate
a false error for the following condition.
3) BUFG feed from a CLKDLL and sourcing a CLKDLL is not on the same edge
This is an allowed connection and used commonly for 4X clock multiplication.
There is a work-around for this case, but it should only be used for this
specific case since it will also disable checks 1 and 2 above.
1) Set the variable NO_GCLKSDLLS_PLACEMENT equal to 1
2) Explicitly LOC all DLL related cells in the UCF,NCF or PCF file.
End of Record #6984 - Last Modified: 09/09/99 09:52 |
