Answers Database 2.1i Virtex PAR - Placer can not successfully place DLL configurations that worked in 1.5i. Record #6986 Product Family: Software Product Line: FPGA Implementation Product Part: par Product Version: 2.1i Problem Title: 2.1i Virtex PAR - Placer can not successfully place DLL configurations that worked in 1.5i. Problem Description: ERROR:Place:1631 - Could not find a legal placement for the following     components:      CLK      I_CG1/CLKDLL1      I_CG1/BUFG1      I_CG1/CLKDLL2      I_CG1/BUFG2 ERROR:Place:1632 - Xilinx requires that such connected GCLK/GCLKIO/DLL components be placed on the same chip edge. Current design constraints do not The placer will not place related DLLs on the different chip edges in cases where 1.5i would handle this configuration. The connection in question is a BUFG driving a DLL CLKIN pin on the other side of the chip. Solution 1: A work around for this problem is to: 1) setenv NO_GCLKSDLLS_PLACEMENT 1 (work station)      set NO_GCLKSDLLS_PLACEMENT=1 (PC) 2) LOC all DLL related comps in the .pcf This issue is being investigated for a possible service pack fix. End of Record #6986 - Last Modified: 08/17/99 18:23

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