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Foundation1.5is2,FPGAExpress3.1: How to get report of synthesis result in Foundation HDL macros
Record #7006
Problem Title:
Foundation1.5is2,FPGAExpress3.1: How to get report of synthesis result in Foundation HDL
macros
Problem Description:
Urgency: Standard
General Description:
In Foundation standard with Express package (FND-EXP),
the tool will report synthesis result such as Primitive reference
count in HDL flow (top level HDL) only. How do you get report
of synthesis result of your HDL macro in a schematic design ?
Solution 1:
1) In HDL editor click on
Synthesis -> Options, and check on the box next to "Show Constraint Editor"
2) After synthesizing your module as a macro, you can find the report of the synthesis result as :
<Project>\DPMCOMP.TMP\chips\<modulenae>_OPT\<modulename>OPT.trt
E.G., If your project name is "test" and the module name
is "bla" the report file will be
test\DPMCOMP.TMP\chips\bla_OPT\bla_OPT.trt file.
NOTE: The trt file is generated only when you specify to show the
constraint editor. Thus FND-BSX package do not have this feature.
End of Record #7006 - Last Modified: 07/14/99 15:59 |
