Answers Database
2.1i; Timing Analyzer: Maximum Delay Path does not match Minimum Period value in Unconstrained section of Unconstrained Report
Record #7013
Product Family: Software
Product Line: FPGA Implementation
Product Part: Timing Analyzer
Product Version: 2.1i
Problem Title:
2.1i; Timing Analyzer: Maximum Delay Path does not match Minimum Period value in
Unconstrained section of Unconstrained Report
Problem Description:
Urgency: Standard
General Description:
Examining an Unconstrained Report, in the Unconstrained
section, shows that the reported maximum delay path is
less than the minimum period. By definition, the maximum
delay path should be the same as the minimum period. The
user instructs the software to keep the longest five path
delays.
Solution 1:
Check to see if there are any two-phase clocks in the design.
For example, if the period is 50 ns, then the total delay will be
50 ns x 2 = 100 ns to account for the two-phase clock in the
design.
Thus, if the highest reported delay is 75 ns, a user would
need to report much more than just five delays in order to
see the two-phase clock at 50 ns since delays are
reported in order from longest to smallest.
End of Record #7013 - Last Modified: 07/14/99 08:46 |
