Answers Database
2.1i Virtex PAR - ERROR:Place:1631, 1632 Could not find a legal placement for the following components....
Record #7025
Product Family: Software
Product Line: FPGA Implementation
Product Part: par
Product Version: 2.1i
Problem Title:
2.1i Virtex PAR - ERROR:Place:1631, 1632 Could not find a legal placement for the following
components....
Problem Description:
Urgency: Standard
General Description:
A design with clkdll's may have gone through the implementation tools with no
errors in 1.5i, but now in 2.1i the following errors show:
ERROR:Place:1631 - Could not find a legal placement for the following
components:
mem1_rac_ctm
clocks/dll_rclk
clocks/bufg_rclk
clocks/bufg_pclk
clocks/dll_iclk
clocks/bufg_iclk
ERROR:Place:1632 - Xilinx requires that such connected GCLK/GCLKIO/DLL
components be placed on the same chip edge. Current design
constraints do not allow this.
Solution 1:
Solution:
These new error messages are for checking the validility of the IBUFG, CLKDLL
and BUFG placement. The M1.5i tools did not check on the placement and allowed
some unstable placements to exist. These new checks have the following rules:
1) IBUFGs must be on the same edge as the CLKDLL that they drive.
2) BUFGs must be on the same edge as the source CLKDLL.
Violating these rules will generate a bad CLKDLL circuit.
There is however an problem that was missed in the new check that will generate
a false error for the following condition.
3) BUFG feed from a CLKDLL and sourcing a CLKDLL is not on the same edge
This is an allowed connection and used commonly for 4X clock multiplication.
There is a work-around for this case, but it should only be used for this
specific case since it will also disable checks 1 and 2 above.
1) Set the variable NO_GCLKSDLLS_PLACEMENT equal to 1
2) Explicitly LOC all DLL related cells in the UCF,NCF or PCF file.
This problem will be fixed in the first major release (as yet unnamed)
following version 2.1i.
End of Record #7025 - Last Modified: 09/09/99 09:58 |
