Answers Database
V1.5 COREGEN: problems with Delay Element locking up and providing only 2 clock delays due to illegal state in LFSR
Record #7084
Product Family: Software
Product Line: LogiCore
Product Part: Coregen IP Modules
Problem Title:
V1.5 COREGEN: problems with Delay Element locking up and providing only 2 clock delays due
to illegal state in LFSR
Problem Description:
Urgency: standard
General Description:
COREGEN Delay Element may delay for 2 clock cycles
less than the user-specified number of cycles under
some conditions.
Solution 1:
The Delay Element delivered during the Coregen 1.5 timeframe
consists of a registered RAM module, and an LFSR counter,
which generates the addresses for the RAM.
The LFSR in this Core may occasionally initialize to an illegal state
of "11" after GSR is released. The problem appears to be associated
with excessive skew (~15ns or more) in the GSR net delays between
the flip-flops in the device in the presence of a free-running clock.
This means that typically only some of the Delay Elements in a user's
design will show the problem.
(In one instance the GSR to clock delay was about 30ns
on the device, compared to the 13ns delay of the free-running
75 MHz clock clocking the circuit.
The LFSR is not able to recover from the "11"
state because the next state for "11" is not defined in the
logic. As a result, only 2 clock cycle delays ended up being added
by the Delay Element--one by the RAM, and the other
by the RAM's output register.
This problem has been fixed in the version of the Delay Element
delivered with the 2.1i version of the CORE Generator.
In addition, several other workarounds are possible:
1. Assert GSR synchronously after the chip comes out of
configuration. (This workaround does not require modification of the
module, but will only work on systems with clocks slower than about
10 MHz.)
2. Add circuitry to the EDIF to reset the LFSR whenever
it reaches the "11" state. (This is somewhat difficult
to do.)
3. In the case of a 4-cycle Delay Element, the XNOR gate which is
sourced by the two flip-flops can be replaced by a NOR gate by
editing the EDIF netlist for that element.
4. Instead of using the Delay Element, connect up a down
counter to a registered RAM with logic to detect
(Terminal Count-1).
5. Instead of using the Delay Element, use a Shift Register.
This is less efficient resource-wise, however.
End of Record #7084 - Last Modified: 07/23/99 10:33 |
