Answers Database
V2.1i COREGEN, SYNPLICITY: CORE Generator does not write out a "/* synthesis black_box */ compiler directive to .VEO file for Synplicity Verilog designs
Record #7119
Product Family: Software
Product Line: Coregen
Product Part: Coregen
Product Version: 2.1
Problem Title:
V2.1i COREGEN, SYNPLICITY: CORE Generator does not write out a "/* synthesis black_box */
compiler directive to .VEO file for Synplicity Verilog designs
Problem Description:
Urgency: standard
General Description:
When Synplicity is specified as the Vendor in the CORE Generator,
the "//synthesis black_box" compiler directive is not written to the .VEO
file.
Solution 1:
The /* synthesis black_box */ directive is a Synplicity-specific directive
that is currently not supported in the 2.1i CORE Generator .VEO file.
The Vendor setting in the Project Options menu only directs CORE
Generator to write out the EDIF implementation netlist for the module
with the appropriate EDIF bus delimiter
Customers must continue to add the /* synthesis black_box */ directive to
their designs manually for now.
This directive should not be confused with the "// synopsys translate_off"
and ''//synopsys translate_on" directives. These latter directives are
used to specifiy that the indicated sections of the .VEO file are for
behavioral simulation only, and should not be compiled when
synthesizing the design.
End of Record #7119 - Last Modified: 07/27/99 16:40 |
