Answers Database
FPGA Express 3.3: How to infer ROM for Virtex
Record #7140
Problem Title:
FPGA Express 3.3: How to infer ROM for Virtex
Problem Description:
Urgency: Standard
General Description:
FPGA Express 3.3 has the ability to infer ROM primitives for Virtex designs if the following syntax
is used. Three points must be noted:
1. Be sure to define all 32 states explicitly. If one state is left out (even if the default case
is
used), standard combinatorial logic algorithms will be used. The when others / default clause
may only be used for the last ("11111") state.
2. These components will be written into the EDIF netlist as LUT4s, not ROM16X1s. Either one
would be implemented identically.
3. This feature is only applicable to Virtex-based architectures.
Solution 1:
The following VHDL code will be implemented in eight LUTs (two for each output bit).
process (ADDRESS)
begin
case ADDRESS is
when "00000" => output <= "1110" ;
when "00001" => output <= "0100" ;
when "00010" => output <= "1101" ;
when "00011" => output <= "0001" ;
when "00100" => output <= "0010" ;
when "00101" => output <= "1111" ;
when "00110" => output <= "1011" ;
when "00111" => output <= "1000" ;
when "01000" => output <= "0011" ;
when "01001" => output <= "1010" ;
when "01010" => output <= "0110" ;
when "01011" => output <= "1100" ;
when "01100" => output <= "0101" ;
when "01101" => output <= "1001" ;
when "01110" => output <= "0000" ;
when "01111" => output <= "0111" ;
when "10000" => output <= "0000" ;
when "10001" => output <= "1111" ;
when "10010" => output <= "0111" ;
when "10011" => output <= "0100" ;
when "10100" => output <= "1110" ;
when "10101" => output <= "0010" ;
when "10110" => output <= "1101" ;
when "10111" => output <= "0001" ;
when "11000" => output <= "1010" ;
when "11001" => output <= "0110" ;
when "11010" => output <= "1100" ;
when "11011" => output <= "1011" ;
when "11100" => output <= "1001" ;
when "11101" => output <= "0101" ;
when "11110" => output <= "0011" ;
when "11111" => output <= "1101" ;
when others => output <= "1101";
end case;
end process;
Solution 2:
The following Verilog code will be implemented in eight LUTs (two for each output bit).
always@(address)
begin
case (address)
5'b00000: romout = 4'b1110;
5'b00001: romout = 4'b0100;
5'b00010: romout = 4'b1101;
5'b00011: romout = 4'b0001;
5'b00100: romout = 4'b0010;
5'b00101: romout = 4'b1111;
5'b00110: romout = 4'b1011;
5'b00111: romout = 4'b1000;
5'b01000: romout = 4'b0011;
5'b01001: romout = 4'b1010;
5'b01010: romout = 4'b0110;
5'b01011: romout = 4'b1100;
5'b01100: romout = 4'b0101;
5'b01101: romout = 4'b1001;
5'b01110: romout = 4'b0000;
5'b01111: romout = 4'b0111;
5'b10000: romout = 4'b0000;
5'b10001: romout = 4'b1111;
5'b10010: romout = 4'b0111;
5'b10011: romout = 4'b0100;
5'b10100: romout = 4'b1110;
5'b10101: romout = 4'b0010;
5'b10110: romout = 4'b1101;
5'b10111: romout = 4'b0001;
5'b11000: romout = 4'b1010;
5'b11001: romout = 4'b0110;
5'b11010: romout = 4'b1100;
5'b11011: romout = 4'b1011;
5'b11100: romout = 4'b1001;
5'b11101: romout = 4'b0101;
5'b11110: romout = 4'b0011;
5'b11111: romout = 4'b1101;
default: romout = 4'b1101;
endcase
end
End of Record #7140 - Last Modified: 01/04/00 12:05 |
