Answers Database
2.1i Virtex Map - Can any component drive the CLKIN input of a clkdll?
Record #7147
Product Family: Software
Product Line: FPGA Implementation
Product Part: map
Product Version: 2.1i
Problem Title:
2.1i Virtex Map - Can any component drive the CLKIN input of a clkdll?
Problem Description:
Urgency: Standard
General Description: Can any net in the design drive the clkin input of a clkdll?
Solution 1:
In 2.1i, the only valid components that can drive the CLKIN pin of the dll
are an IPAD, BUFG, or IBUFG.
Solution 2:
This is a valid error because if the CLKIN is driven by a non BUFG/IBUFG,
we cannot guarantee a proper phase relationship to the original clock and
timing analysis results will not be valid. This is consistent with the App Note
(Xilinx XAPP# 132).
However... there are valid reasons for wanting to do this and the common
one is clock doubling where phase relationship to original clock doesn't
matter. The next release after 2.1i will support this under environment variable
control, and it will also change the error message to indicate that such an env
var exists, but to warn the user that timing analysis results will no longer be
valid for paths affected by the output of this DLL.
End of Record #7147 - Last Modified: 01/05/00 10:48 |
