Xilinx Answer #7152 : LogiCORE PCI64 Virtex (v3.x): Plugging a 64-bit card in a 32-bit slot

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LogiCORE PCI64 Virtex (v3.x): Plugging a 64-bit card in a 32-bit slot

Record #7152
Product Family: Documentation

Product Line: PCI Apps

Product Part: PCI Design Solutions

Problem Title:
LogiCORE PCI64 Virtex (v3.x): Plugging a 64-bit card in a 32-bit slot

Problem Description:
Urgency: Standard

General Description:

The PCI spec allows a 64-bit card to be plugged into a 32-bit slot for the
sake of backward compatibility. To determine bus width during system
initialization, the spec calls for agents to sample REQ64# during PCI
Reset. The central resource must drive REQ64# low during the time
RST# is asserted. Devices that see REQ64# asserted on the rising edge
of RST# are connected to the 64-bit data path. According to the spec, the
RST# pulse can be asserted for 1ms. However, an FPGA may have
difficulty in sampling a REQ64# signal during this timeframe as it may not
fully configure before RST# is de asserted.

The LogiCORE PCI interface uses an input called SLOT64 to determine
whether it is plugged into a 64-bit or 32-bit slot. The user application
should drive this input with a fixed value from the output of a flip-flop
except during PCI reset.

What are the possible methods of driving SLOT64?

Note: An Engineering Change Request that specifies a sufficient length
for the RST# pulse is pending before the PCI SIG.

Solution 1:

Open Systems:

The end user can set the state of SLOT64 by using a jumper when
installing the product. This method is simple, but error prone.

Solution 2:

Open Systems:

The designer can use a flip-flop external to the FPGA to sample
REQ64#.

Using an external flip-flop to drive SLOT64

This technique is not technically compliant with the PCI spec as it
causes extra loading on REQ64# and RST#. However, using a large
series resistor can minimize the loading effects. The inverter may be
pushed into the FPGA.

Solution 3:

Embedded Systems:

The bus width here is pre-determined as the system is closed. The
designer can drive SLOT64 from the output of a flip-flop set high upon
PCI reset.

Solution 4:

Open Systems:

The designer can push a flip-flop inside the FPGA to sample REQ64#

Using a flip-flop inside the FPGA to drive SLOT64

The designer must make sure that the FPGA downloads the bitstream
quickly enough. Even though the spec mentions that the RST# time is 1ms,
for practical purposes, systems require ~20ms to come out of reset. The
20ms value can be used as a good rule of the thumb. This is the
recommended method when using small to medium sized devices with
fast FPGA configuration modes.

Note: For this solution to work, the following modifications must be made to the placed and routed NCD file using FPGA Editor -

1. Find the location constraint (site) for the NET named PCI_CORE/REQ64_IO
     from constraint file (UCF) supplied with the LogiCORE PCI interface.
2. Open the pcim_top_routed.ncd file in FPGA editor
3. Find the relevent site in the FPGA editor. Turning the FPGA Editor text option
     on should display the text "REQ64_N".
4. Select this block and click on the editblock button.
5. Search for the IFF in this block and turn off the RESET (INIT) line. Leave the
     rest of the RESETs untouched.
6. Save and exit FPGA Editor.
7. Run bitgen on the modified NCD file.

End of Record #7152 - Last Modified: 10/25/99 11:57

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