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FPGA Express: VHDL Error: Range 'U' to 'X' (or 'Z' to '-') not covered by choices. (VSS-838)


Record #7158

Problem Title:
FPGA Express: VHDL Error: Range 'U' to 'X' (or 'Z' to '-') not covered by choices. (VSS-838)




Problem Description:
Urgency: Standard

General Description:
When checking syntax of a VHDL code block for inference of a multiplexer,
port defined as:
      MUX_CTRL: in STD_LOGIC;
code within process statement:
    case MUX_CTRL is
       when '0' =>
      <<do_something>>;
       when '1' =>
      <<do_something_else>>;
    end case;

FPGA Express gives the following error:
Error:	Range 'U' to 'X' not covered by choices. (VSS-838)  (FE-dm-hdlc-unknown)
Error:	Range 'Z' to '-' not covered by choices. (VSS-838)  (FE-dm-hdlc-unknown)


Solution 1:

The reason for this is that all possible values of STD_LOGIC were not covered by the case statement. There are more values possible for STD_LOGIC other than just '0' and '1' like 'U', 'X', 'Z', '-' which need to be covered. Simply add to the end of the case statement:

   when others => null;

Preferably, this will take the place of the last comparison in the case statement.

The following is the case statement code given in the HDL Editor language assistant:

   case <expression> is
      when <choices> =>
	 <statements>
      when <choices> =>
	 <statements>
      when others =>
	 <statements>
   end case;
   -- example:
   --case SEL is
   --	when 0 | 1 | 2 =>
   --	   Z <= B;
   --	when 3 to 10 =>
   --	   Z <= C;
   --	when others =>
   --	   null;
   --end case;




End of Record #7158 - Last Modified: 09/01/99 15:11

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