Answers Database Virtex JTAG - How to perform a Readback Verify on the Virtex devices? Record #7172 Product Family: Hardware Product Line: Virtex Product Part: Virtex General Hardware Problem Title: Virtex JTAG - How to perform a Readback Verify on the Virtex devices? Problem Description: Urgency: Hot General Description: What are the steps required to do a readback on the Virtex devices? Solution 1: To perform a readback you need to follow the following steps using your own software: 1) Load in the CFG_IN instruction into the JTAG IR and then go to SDR. 2) Shift in a packet to write the starting frame address into the FAR. For a full-chip readback this is frame 0 of CLB column 0. 3) Shift in a packet to write the RCFG command into the CMD register. 4) Shift in a packet header requesting a read of the Frame Data Output   Register (FDRO). The word count should reflect the number of frames   you wish to read. If the number of words exceeds 2048 you must use   a two part header (i.e., Type I followed by Type II). 5) Shift in an extra 32 bits. These are to flush the pipeline through   the packet processor. Then go back to RTI. 6) Load the CFG_OUT instruction into the JTAG IR and then go to the SDR. 7) Clock TCK and read TDO. There will be a few 32-bit words of garbage before the readback data appears. 8) If you wish to read the Block RAM (BRAM) data as well as the CLB data you should repeat 1-7 substituting the appropriate BRAM address for the starting CLB address. Each BRAM must be addressed individually. Note that reading back the BRAM will interface with BRAM operation in an active system. It is therefore recommended that the system be halted prior to BRAM readback. End of Record #7172 - Last Modified: 01/26/00 15:19

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