Answers Database LogiCORE PCI: Base Address Registers (BAR's) and configuration accesses in a PCI system Record #7176 Problem Title: LogiCORE PCI: Base Address Registers (BAR's) and configuration accesses in a PCI system Problem Description: Urgency: Standard General Description: What is the basic methodology for setting up Base Address Registers in a PCI system? Solution 1: The Base Address Registers (BAR) are used if the PCI agent needs to utilize some memory or I/O address space. It is a 32-bit register in the Configuration Space, the first of which begins at address 0x04. In the Xilinx PCI LogiCore, the cfg.v or cfg.vhd has information as to what size and type of BAR is implemented: `define ENABLE 1'b1 `define SIZE16M 32'hff00_0000 `define NOFETCH 1'b0 `define TYPE00 2'b00 `define MEMORY 1'b0 // BAR0 assign CFG[0] = `ENABLE ; assign CFG[32:1] = `SIZE16M ; assign CFG[33] = `NOFETCH ; assign CFG[35:34] = `TYPE00 ; assign CFG[36] = `MEMORY ; For more information on the Base Address Register, please refer to section 6.2.5 of the PCI Local Bus Specification, version 2.2. When the system is powered up, the host needs to determine what memory size the PCI agent needs, and it needs to assign it a starting address. The former is accomplished by writing 0xFFFFFFFF to the BAR, and then reading back the same BAR.In the above example, when the BAR is read back, it will return 0xFF000000. The lowest four bits are for Prefetch, Type, and Type Indicator. The middle 20 bits are hardwired to 0, for reasons explained below. This signals to the host that only the top 8 bits are writable. The host will then allocate 16 MB of memory space, and write the BAR, this time giving it a valid address. For example: 0xAA00000000. This tells the agent that its 16 MB of memory space begins at the address AA00000000. According to the PCI specification, all address spaces must be naturally aligned, so it is not possible to have a 16 MB address space begin at a memory address not divisible by 16 MB. This is why the middle 20 bits would be hardwired to 0- the host needs to know what the size is, and the agent would not need those bits to store an address. For a memory BAR, the smallest possible size would leave [31:4] writable, which would be 16 bytes. By the same token, the largest size would only have bit 31 writable, which corresponds to a 2 GB size. Since I/O BAR's only need the two LSB's for type indication, the smallest size would be 4 bytes. According to the PCI spec, the largest I/O size is 256 bytes. End of Record #7176 - Last Modified: 09/15/99 13:31

For the latest news, design tips, and patch information on the Xilinx design environment, check out the Technical Tips!