Answers Database
2.1i Virtex MAP Error:xvkpu - Unable to obey design constraints
Record #7222
Product Family: Software
Product Line: FPGA Implementation
Product Part: map
Product Version: 2.1i
Problem Title:
2.1i Virtex MAP Error:xvkpu - Unable to obey design constraints
Problem Description:
Urgency: Standard
General Description:
In a v300 design in which fmaps are used to insert multiple buffers to
create delay and a KEEP attribute is placed on the net between the
two buffers as well as on the net of the output of the second buffer,
the following error in map occurs:
ERROR: xvkpu - Unable to obey design constraints (MACRONAME = U9/hset, RLOC = ROCO.S1)
which require the combination of the following symbols into a single slice:
LUT symbol "u9/Q38" (Output Signal = U9/A8)
LUT symbol "u9/Q49" (Output Signal = U9/X7D)
Signal 'U9/X7D' has a NOMERGE parameter.
Solution 1:
Workaround:
Remove the keep attribute between the two buffers.
End of Record #7222 - Last Modified: 12/21/99 14:40 |
