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Foundation 2.1i, FPGA Express 3.2: Is it possible to infer signed arithmetic modules in VHDL or Verilog?
Record #7240
Product Family: Software
Product Line: Synopsys
Product Part: FPGA Express
Product Version: 3.2
Problem Title:
Foundation 2.1i, FPGA Express 3.2: Is it possible to infer signed arithmetic modules in VHDL
or Verilog?
Problem Description:
Urgency: Standard
General Description:
Is it possible to infer signed arithmetic modules in VHDL or Verilog?
Solution 1:
For VHDL, signed modules can be inferred but currently it is not possible to infer
both signed and unsigned operators in the same entity-architecture pair.
Please see the FPGA Express online help topic "Arithmetic and Relational Module
Inference Examples" for examples and more information.
Solution 2:
Currently, it is not possible to infer signed modules in Verilog.
For more information please refer to the FPGA Express online help topic
"Arithmetic and Relational Module Inference Examples".
End of Record #7240 - Last Modified: 08/30/99 15:23 |
