Answers Database
FPGA Express: Is there an option to disable carry logic?
Record #7262
Problem Title:
FPGA Express: Is there an option to disable carry logic?
Problem Description:
Urgency: Standard
General Description:
Is there an option to disable carry logic when synthesizing HDL for XC4000, Spartan
and Virtex architectures?
Solution 1:
There is no way to disable the inference of carry logic when synthesizing arithmetic
functions using FPGA Express. As long as arithmetic operators are used in your HDL
code, carry logic will be inferred.
End of Record #7262 - Last Modified: 08/17/99 14:56 |
