Answers Database


FPGA Express: BSCAN_VIRTEX is removed from the design without warning


Record #7291

Product Family: Software

Product Line: Synopsys

Product Part: FPGA Express

Product Version: 3.2

Problem Title:
FPGA Express: BSCAN_VIRTEX is removed from the design without warning


Problem Description:
Urgency: Standard

General Description:
FPGA Express may remove the BSCAN_VIRTEX from the design before optimization. The can occur in VHDL or Verilog designs, and may happen with other architecture-specific, non-synthesizable components like CAPTURE_VIRTEX or STARTUP_SPARTAN2.


Solution 1:

VHDL:

If this occurs in a VHDL design, place a dont_touch attribute on the instantiation in the HDL code to prevent it from being removed. This must be done within the code as opposed to with the FPGA Express Constraints Editor, as the component is removed before the attribute can be applied within the Editor.


...

component BSCAN_VIRTEX port
     (TDO1, TDO2 : in STD_LOGIC;
      RESET, UPDATE, SHIFT, DRCK1, DRCK2, SEL1, SEL2, TDI : out STD_LOGIC );
end component;
attribute fpga_dont_touch : string;
attribute fpga_dont_touch of U1 : label is "true";

begin
U1 : BSCAN_VIRTEX  port map
   (TDO1 => TDO1, TDO2 => TDO2, RESET => RESET, UPDATE => UPDATE, SHIFT => SHIFT,
      DRCK1 => CLK1, DRCK2  => CLK2, SEL1 => SEL1, SEL2 => SEL2, TDI => TDI);
...



Solution 2:

Verilog:

If this occurs in a Verilog design, create an empty module declaration for the component being removed. This will define the port directions and allow Express to insert the component correctly.


...
BSCAN_VIRTEX U1
      (.TDO1(TDO1), .TDO2(TDO2), .RESET(RESET), .SHIFT(SHIFT), .UPDATE(UPDATE),
       .DRCK1(CLK1), .DRCK2(CLK2), .SEL1(SEL1),  .SEL2(SEL2), .TDI(TDI));
...
endmodule

module BSCAN_VIRTEX
      (TDO1, TDO2, RESET, SHIFT, UPDATE, DRCK1, DRCK2, SEL1,  SEL2, TDI);
input TDO1, TDO2;
output RESET, SHIFT, UPDATE, DRCK1, DRCK2, SEL1,  SEL2, TDI;
endmodule




End of Record #7291 - Last Modified: 01/20/00 11:00

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