Answers Database
2.1i Virtex PAR - Placer has been enhanced to use MAXSKEW preference to assign secondary global clock buffers for external clock nets.
Record #7316
Product Family: Software
Product Line: FPGA Implementation
Product Part: par
Product Version: 2.1i
Problem Title:
2.1i Virtex PAR - Placer has been enhanced to use MAXSKEW preference to assign secondary
global clock buffers for external clock nets.
Problem Description:
Urgency: Standard
General Description:
Previous to the 2.1i Service Pack 1 Update, secondary global clock resource
usage could not be controlled by the user, but were assigned automatically by
the tools.
The secondary clock resource usage is now triggered by use of a MAXSKEW
constraint. All internally generated clocks however will not be guaranteed to use
the secondary clock resources.
A workaround is to place the CLB generating such signals/clocks on the
top or bottom row of the device. Placing them on the top or bottom row enable
the router to use the secondary clock routing.
Solution 1:
This problem is fixed in the latest 2.1i Service Pack available at:
http://support.xilinx.com/support/techsup/sw_updates/
Solution 2:
A new feature will be available in the next (as yet unnamed) release
following 2.1i that will support the use of a new NET constraint
USELOWSKEWLINES to assign the usage of secondary clock routing
resources to specific nets.
Example of UCF syntax:
NET "NET_NAME" USELOWSKEWLINES" ;
End of Record #7316 - Last Modified: 12/21/99 12:32 | 
