Answers Database 2.1i 9500/XL: Hitop (CPLD Fitter) not fitting DFF--> INV --> OBUF correctly Record #7337 Product Family: Software Product Line: CPLD Implementation Product Part: hitop Product Version: 2.1i Problem Title: 2.1i 9500/XL: Hitop (CPLD Fitter) not fitting DFF--> INV --> OBUF correctly Problem Description: Urgency: Hot General Description: The circuit in question is a D-FF with asynchronous clear, the output of which is inverted at the pin. In addition the non-inverted output signal (RAS) is fed back into the internal logic. The effect of RESET is to clear the register, which due to the inversion causes /RAS0 to be asserted (high). Thus the fitter must convert the CLEAR into a PRESET when it moves the inversion to the input side of the FF. However, the report file shows the following equations for /RAS0: /"/ras0" := /"B1/LBANK1" * "B1/STATE0" * "B1/STATE2" *       ... snip...      "/ras0".CLKF = CLOCK ;FCLK/GCK      "/ras0".RSTF = /"/reset" ;GSR      "/ras0".TRST = OUTENB ;FOE      "/ras0".PRLD = GND These equations indicate that the output "/ras0" will be _cleared_ (low) when the reset signal is asserted (the .PRLD should also be high (VCC)). A similarly implemented signal is correctly reported as: /"/pciack" := "/ms0" * /"B1/BUSY" * /"B1/RFSH" * /"B1/STATE2" * ... snip ... "/pciack".CLKF = CLOCK ;FCLK/GCK "/pciack".SETF = /"/reset" ;GSR "/pciack".TRST = /"/pcireq" "/pciack".PRLD = VCC Note that .SETF is used for RESET and .PRLD is high (VCC) as expected. The bug will be triggered every time a register with a set/rst signal drives an inverter which in turn drives an OBUFT. In this case the software will not swap the set/rst when the inverter is swallowed by the register. Solution 1: This problem has been fixed in the latest 2.1i Service Pack available at: http://support.xilinx.com/support/techsup/sw_updates End of Record #7337 - Last Modified: 12/30/99 14:10

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