Answers Database


Virtex CLKDLL: Will the CLKDLL lock if the input frequency is below 25Mhz, if not, what would the outputs of the CLKDLL be like.


Record #7402

Product Family: Hardware

Product Line: Virtex

Product Part: Virtex General Hardware

Problem Title:
Virtex CLKDLL: Will the CLKDLL lock if the input frequency is below 25Mhz, if not, what would the outputs of the CLKDLL be like.



Problem Description:
Urgency: Standard

Problem description:

If the input to the CLKDLL is less than 25Mhz, will the CLKDLL lock, and what will the outputs of the CLKDLL be like


Solution 1:

If the input frequency of the CLKDLL is less than 25Mhz, CLKDLL will not lock.
The CLKDLL will continous try to achieve lock on the CLKIN signal
and the output will slew in phase, period and duty cycle as the control
logic attempts to lock on the input clock.






End of Record #7402 - Last Modified: 01/25/00 09:34

For the latest news, design tips, and patch information on the Xilinx design environment, check out the Technical Tips!