Answers Database
FPGA Express: Express does not know about dedicated clock pads
Record #7411
Product Family: Software
Product Line: Synopsys
Product Part: FPGA Express
Product Version: 3.2
Problem Title:
FPGA Express: Express does not know about dedicated clock pads
Problem Description:
Urgency: Standard
General Description:
FPGA Express does not have detailed information about Xilinx chip pinouts.
When a clock buffer is inserted in a design, either by inference, instantiation, or
via the constraints editor, FPGA Express does not know if you will be using a
dedicated clock pad or not, even if you assign the pin location constraint within
Express.
If you do not use a dedicated clock pin on the chip, you will receive the
following error in map:
Error in map 2.1i:
ERROR:OldMap:56 - The LOC constraint "P28" (a IOB location) is not valid for
symbol "Clk.PAD" (pad signal=Clk), which is being mapped to the following
site types:
CLKIOB
Solution 1:
The solution is to instantiate BOTH an IBUF and BUFG in series in your HDL code
(port -> IBUF -> BUFG -> clock pins). Express will leave this combination intact and
the implementation tools will be able to route this using a non-dedicated IOB.
End of Record #7411 - Last Modified: 09/01/99 11:26 |
