Answers Database
Virtex Configuration: Initialization timing for SelectMap (CS/ assertion)
Record #7412
Product Family: Hardware
Product Line: Virtex
Product Part: Virtex General Hardware
Problem Title:
Virtex Configuration: Initialization timing for SelectMap (CS/ assertion)
Problem Description:
Urgency: Standard
General Description: What is the necessary initilization timing to configure a Virtex device in Sel
ectMAP mode?
Solution 1:
This Answer will address some confusion with the timing of CS/ and the first writing of a data wor
d. For in depth
discussion of Virtex configuration issues, please refer to (Xilinx XAPP138)
Following power up, the Virtex device requires three clock cycles to initialize. If a data write
is attempted before
this initialization, no data will be transferred. It could appear at first glance that data isn't b
eing written until the
second rising CCLK after CS/ is asserted, which seems to contradict XAPP138. However, the waveforms
for
SelectMAP and serial modes assume that it is a bitgen-generated bitstream that is being loaded. Thi
s bitstream
has 32 bits of padding at the beginning of it, so even if a bit or byte (or two) is ignored because
of this initialization
timing, no ill effects will result.
End of Record #7412 - Last Modified: 11/23/99 10:15 |
