Answers Database
LogiCORE PCI: The PCI master may stop bursting data after 2 clocks during simulation
Record #7413
Problem Title:
LogiCORE PCI: The PCI master may stop bursting data after 2 clocks during simulation
Problem Description:
Urgency: Standard
General Description:
The PCI master may stop bursting data after two PCI clocks even though the user app desires
to transfer multiple DWORDS during simulation. What is the cause of this behavior?
Solution 1:
The length of the burst is controlled by the Latency Timer in the PCI configuration header.
In a real PCI system, this value is set by the OS. However, during simulation, this value
must be set by the user using a command such as the WRITE_CONFIG command
provided with the test bench. The user will have to modify the stimulus.v/vhd files to set
the Latency Timer.
Adding a WRITE_CONFIG statement as shown below will set the Latency timer to the
maximum value.
-- setup MLT to maximum value
WRITE_CONFIG( X"0000000C", X"0000ff00");
Note that this statement will also write to the BIST, Header Type and Cache Line Size
registers in the configuration header. However, these registers are hard-coded in the
LogiCORE PCI Interface and can not be set/reset with a CONFIG_WRITE command.
The user should experiment with the Latency Timer value to get an optimum result.
End of Record #7413 - Last Modified: 08/30/99 17:57 |
