Answers Database
How to set the CLKDV_DIVIDE property for the CLKDLL
Record #7419
Product Family: Hardware
Product Line: Virtex
Product Part: Virtex General Hardware
Problem Title:
How to set the CLKDV_DIVIDE property for the CLKDLL
Problem Description:
Urgency : standard
General Description : The CLKDV output of a clkdll can take divisor of
1.5,2,2.5,3,4,5,8,16. The default is 2. In order to change the value, the
CLKDV_DIVIDE property needs to be changed to a new value.
Solution 1:
The syntax you can add to the UCF is :
INST <CLKDLL_name> clkdv_divide = N;
Where N = the divisor value
<CLKDLL_name> is the instance name.
Solution 2:
It is also possible to place the CLKDV_DIVIDE attribute in the VHDL
code if the synthesis tool allows attribute passing. The general
syntax for this is:
VHDL
place the following in the architecture before the "begin" keyword:
attribute <name> : string;
attribute <name> of <instance> : label is <value>;
Example VHDL code portion:
attribute CLKDV_DIVIDE: string;
attribute CLKDV_DIVIDE of U1: label is "1.5";
begin
U1 : CLKDLL port map(
CLKIN => CLK,
RST => RST,
CLKFB => CLKFB,
CLK0 => a,
CLK90 => b,
CLK180 => c,
CLK270 => d,
CLKDV => e,
CLK2x => f,
LOCKED => lock);
Solution 3:
It is also possible to place the CLKDV_DIVIDE attribute in the Verilog
code if the synthesis tool allows attribute passing. The general
syntax for this is (this example is shown for synopsys, if using another
synthesis tool, use the proper syntax for attribute passing in that tool):
Verilog
//synopsys attribute <name> <value>
This comment is placed immediately after the instantiated component
Example Verilog code portion:
CLKDLL U1 (.CLKIN(CLK), .CLKFB(CLKFB), .RST(RST),
.CLK0(a), .CLK90(b), .CLK180(c), .CLK270(d),
.CLK2X(e), .CLKDV(f), .LOCKED(lock));
/* synopsys attribute
CLKDV_DIVIDE "1.5"
*/
End of Record #7419 - Last Modified: 01/18/00 09:30 |
