Answers Database
2.1i COREGEN, ACTIVE-VHDL: Issues compiling the CORE Generator 2.1i VHDL models for the Active HDL simulator
Record #7433
Product Family: Software
Product Line: Coregen
Product Part: Coregen
Product Version: 2.1
Problem Title:
2.1i COREGEN, ACTIVE-VHDL: Issues compiling the CORE Generator 2.1i VHDL models for the
Active HDL simulator
Problem Description:
Urgency: standard
General Description:
Issues compiling the CORE Generator 2.1i VHDL models for the Active HDL
simulator.
This solution contains some tips on compiling the CORE
Generator VHDL library for Active VHDL. For the latest
inforrmation, please contact support@aldec.com directly.
Solution 1:
1. The first issue is associated with a reference to an MTI-specific
"arithmetic" library in the Coregen 2.1i models. The workaround is to
alter the prims_sim_arch.vhd file as described in the following solution record:
http://www.xilinx.com/techdocs/6771.htm
2. The second issue is an Active HDL problem which is flagged by the following
error message:
Error: COMP96_0149: pdafirvht.vhd : (263, 54): Explicit type conversions are allowed
between closely related types only.
The offending line ,
filter_coefficients := filter_coefficients_type(coefficients(0 TO number_of_taps-1));
should be replaced by
FOR i IN 0 TO number_of_taps-1 LOOP
filter_coefficients(i) := coefficients(i);
END LOOP;
3. Although Active HDL claims to support MTI compile syntax, it does not suppor t
wildcards in the arguments to the VCOM command, To compile the Coregen VHDL
models, you will need to specify the name of each VHDL model individually if you
are trying to use an MTI syntax compile script.
End of Record #7433 - Last Modified: 09/20/99 11:20 |
