Answers Database OrCad Express v9.x does not interface correctly with Xilinx A2.1 tools for XC9500 CPLDs Record #7438 Product Family: Software Product Line: CPLD Implementation Product Part: CPLD Product Version: 2.1i Problem Title: OrCad Express v9.x does not interface correctly with Xilinx A2.1 tools for XC9500 CPLDs Problem Description: Urgency: Standard General Description: A customer using OrCad version 9.x in conjunction with A2.1i/F2.1i to create a Jedec file for an XC9500 CPLD will get a message similar to the following in the OrCad Capture Session Log: Running Xilinx Hplusas6...    ************************************************************************ Executing: 'C:\Xilinx_CPLD\bin\nt\hplusas6.exe -i <design_name> -s -a -l Design_name.log -o Timed' ERROR [FPG0004] Unable to run child process, error (2) . . . This will be followed by a Windows application error for the program hprep6.exe Solution 1: There has been a change in the Xilinx CPLD fitter flow in our new Version 2.1i software which has not yet been reflected in the OrCAD tools. We have contacted OrCad and we are working with them to implement this change in the OrCAD tools. In the mean time, the CPLD fitter can be run successfully via the Xilinx Design Manager GUI. Procedure for implementing an XC9500 design using OrCAD 9.x:       1. Produce a netlist for the design using the OrCAD tools and open the        Xilinx Design Manager. This can be done in either of two ways:         Alternative 1 (automated flow):              a) Select TOOLS->Build from the OrCAD project menu. This should               bring up the "Xilinx M1 Build Settings" window.               (Compile the design if prompted to do so.)              b) Under the "General" tab, check the button labeled "Run the Xilinx               Design Manager instead".              c) Select OK. The M1 design manager should then open.         Alternative 2 (direct method):              a) Select TOOLS->Compile from the OrCAD project menu.              b) Invoke the Design Manager by selecting "CPLD Fitter Tools" from               the Xilinx CPLD Webpack program group under the Windows Start               menu.       2. In Design Manager, create a new project:         a) File -> New Project         b) Use Browse to set the Input Design to the EDIF netlist created by             OrCAD (in the design\compile directory). Ok.       3. Select the Part. Ok.       4. Point the Design Manager to OrCAD's CPLD macro library:         a) Select Design -> Options.         b) Select "User Defined" as the CPLD Optimization Style.         c) Click "Edit Options".         d) Go to the Translate tab.         e) Use Browse to set the Macro Search Path to the directory             capture\LIBRARY\XIL_M1\XC9500, where capture is your OrCAD             installation directory.       5. Set any of the other desired fitter options in the Basic and other tabs of        the XC9500 Implementation Options window. Ok.       6. Select a timing simulation output format if desired (Simulation Options). Ok.       7. Select Design Implement to run the fitter. End of Record #7438 - Last Modified: 09/01/99 15:36

For the latest news, design tips, and patch information on the Xilinx design environment, check out the Technical Tips!