Answers Database
2.1i 4K Map - Map can not combine dual port ram with registers into the same CLB when local set /reset signal used.
Record #7478
Product Family: Software
Product Line: FPGA Implementation
Product Part: map
Product Version: 2.1i
Problem Title:
2.1i 4K Map - Map can not combine dual port ram with registers into the same CLB when
local set /reset signal used.
Problem Description:
Urgency: standard
General Description:
When distributed ram is used to generate a dual port RAM, if the output data signal is registered to
enable synchronous reads from the RAM map will not push the register into the same CLB.
Solution 1:
If the register is using a local control signal such as CLR map will be unable to combine the two in
to
one CLB, this is because the CLR signal is brought into the CLB using one of the control signals (SR
)
which has already been used as the write enable in the dual port RAM.
End of Record #7478 - Last Modified: 09/09/99 13:07 |
