Answers Database
2.1i TRCE Spartan\XL: Input hold time using Primary Clock and IFF is non-zero even with delay
Record #7483
Product Family: Software
Product Line: FPGA Implementation
Product Part: trce
Product Version: 2.1i
Problem Title:
2.1i TRCE Spartan\XL: Input hold time using Primary Clock and IFF is non-zero even with
delay
Problem Description:
Urgency: Standard
General Description:
TRCE sometimes reports non-zero values for input
hold time using Primary Clock and IFF ( input Flip-Flop
or Latch) even with delay contrary to Spartan
Pin-to-Pin Input Parameter Guidelines in the data book.
Solution 1:
>This was due to the timing values for these delays is
not supplied in the speed files. On the actual
silicon, the zero hold time is guaranteed as
specified in the data book.
See (Xilinx solution 4823) for how to calculate the setup/hold times.
End of Record #7483 - Last Modified: 01/04/00 10:05 |
