Answers Database
FPGA Express 3.x: Express inverting load/clock signal for 4000/Spartan input latches
Record #7497
Product Family: Software
Product Line: Synopsys
Product Part: FPGA Express
Product Version: 3.2
Problem Title:
FPGA Express 3.x: Express inverting load/clock signal for 4000/Spartan input latches
Problem Description:
Urgency : Standard
General Description:
FPGA Express 3.x incorrectly inverts all load (G input) signals for inferred ILD latches.
This happens when targeting all FPGA devices except for Virtex. When examining the XNF file you
will see a ", INV" on the G pin of the ILD component.
Solution 1:
Several workarounds are available:
-- Instantiate the ILD component
-- Invert the Gate signal before latches that are moved into the IOB
-- Disable the I/O Register Merge feature in the Express Constraints Editor
-- Use registers instead of latches
End of Record #7497 - Last Modified: 11/22/99 10:48 |
