Answers Database
2.1i Virtex Map - Pack of two RAMs into one slice fails with incorrect message.
Record #7638
Product Family: Software
Product Line: FPGA Implementation
Product Part: map
Product Version: 2.1i
Problem Title:
2.1i Virtex Map - Pack of two RAMs into one slice fails with incorrect message.
Problem Description:
Urgency: Standard
General Description:
Error message incorrectly indicates that the address nets are not the same for two
RAM symbols constrained to the same slice.
ERROR:xvkpu - Unable to obey design constraints (MACRONAME = H1/hset, RLOC =
R5C0.S0) which require the combination of the following symbols into a single
slice:
RAM symbol "H1/$I711" (Output Signal = &__A__12)
RAM symbol "H1/$I712" (Output Signal = &__A__11)
The address signals must match exactly when using both F and G in RAM mode.
Solution 1:
This problem is fixed in the latest 2.1i Service Pack available at:
http://support.xilinx.com/support/techsup/sw_updates/
End of Record #7638 - Last Modified: 10/18/99 10:28 |
