Answers Database
2.1i Virtex Map - Unable to pack the register xxx because of connectivity restrictions.
Record #7733
Product Family: Software
Product Line: FPGA Implementation
Product Part: map
Product Version: 2.1i
Problem Title:
2.1i Virtex Map - Unable to pack the register xxx because of connectivity restrictions.
Problem Description:
Urgency: Standard
General Description:
A case has been seen where Map fails to pack two FDRS's with common
set/reset nets. This pack worked in 1.5i.
ERROR:xvkpu - Unable to obey design constraints (MACRONAME = U1/hset, RLOC =
R6C0.S1) which require the combination of the following symbols into a single
slice:
FLOP symbol "U1/$I887" (Output Signal = &__A__16)
FLOP symbol "U1/$I888" (Output Signal = &__A__15)
LUT symbol "U1/$I902" (Output Signal = U1/I2)
MUXCY symbol "U1/$I743" (Output Signal = U1/$I743/O)
MUXCY symbol "U1/$I858" (Output Signal = U1/$I858/O)
LUT symbol "U1/$I796" (Output Signal = U1/I3)
Unable to pack the register U1/$I888 because of connectivity restrictions.
Solution 1:
The problem in this case was that both flops were driven by
non-RLOC'd XORCY components. When combined with the
fact that the flops are using both set and reset, this led map
to incorrectly assume that there was a conflict over the BY input
pin. The work around is to add .ucf file constraints to RLOC
the XORCYs:
INST "U1/$I853" RLOC = "R6C0.S1" ;
INST "U1/$I724" RLOC = "R6C0.S1" ;
Solution 2:
This problem is scheduled to be fixed in the next (as yet unnamed)
release following version 2.1i. This release is currently scheduled
for March, 2000.
End of Record #7733 - Last Modified: 12/13/99 12:53 |
