Answers Database 2.1i Virtex PAR - The .par results file reports incorrect number of logic levels Record #7734 Product Family: Software Product Line: FPGA Implementation Product Part: par Product Version: 2.1i Problem Title: 2.1i Virtex PAR - The .par results file reports incorrect number of logic levels Problem Description: Urgency: Standard General Description: A PAR run is aborted due to timing violations during Initial Timing Analysis. The resulting .par fil e incorrectly reports that there are 2 levels of logic involved. Running TRCE reveals that there are   actually 28 levels of logic involved. From testr.par: -------------------------------------------------------------------------------- * TS01 = MAXDELAY FROM TIMEGRP "CLK_85_6MHZ | 11.628ns | 15.131ns | 2 " TO TIMEGRP "FFS" 11.628 nS | | | -------------------------------------------------------------------------------- From test.twr ================================================================================ Timing constraint: TS01 = MAXDELAY FROM TIMEGRP "CLK_85_6MHZ" TO TIMEGRP "FFS" 1 1.628 nS ; ^M 19684380 items analyzed, 63 timing errors detected. Maximum delay is 15.131ns. -------------------------------------------------------------------------------- Slack: -3.503ns path H60/ABS_Q8 to MAG<18> relative to 11.628ns delay constraint Path H60/ABS_Q8 to MAG<18> contains 28 levels of logic: Path starting from Comp: SLICE.CLK (from CLK_85_6MHZ) To Delay type Delay(ns) Physical Resource                                   Logical Resource(s) ------------------------------------------------- -------- Solution 1: This problem is fixed in the latest 2.1i Service Pack available at: http://support.xilinx.com/support/techsup/sw_updates/ End of Record #7734 - Last Modified: 10/18/99 10:15

For the latest news, design tips, and patch information on the Xilinx design environment, check out the Technical Tips!