Answers Database
2.1i Foundation - LOCKED signal does not go high on CLKDLL during Timing Simulation
Record #7775
Product Family: Software
Product Line: Aldec
Product Part: Foundation Logic Simulator
Product Version: 2.1i
Problem Title:
2.1i Foundation - LOCKED signal does not go high on CLKDLL during Timing Simulation
Problem Description:
Urgency: Standard
General Description: During Timing Simulation of the CLKDLL,
the LOCKED output signal never goes high. This limitation is
the result of simulation resolution in the Foundation Logical
Simulator . Currently the resolution is limited to 100ps. In order
for the CLKDLL to lock the resolution must be set to 1ps.
Solution 1:
There are two workarounds:
1- Manually apply stimulus to the CLKDLL LOCKED signal to
drive it high at 300ns. This will allow more than enough time
to model the LOCKED signal on the board.
2- Use a third party simulator such as Modelsim where the
resolution can be set to 1ps.
End of Record #7775 - Last Modified: 12/10/99 06:32 |
