Answers Database
LogiCORE PCI: Simulating the LogiCORE PCI interface in VHDL causes some back-end signals to go unknown
Record #7779
Product Family: Documentation
Product Line: PCI Apps
Product Part: PCI Frequently Asked Questions
Problem Title:
LogiCORE PCI: Simulating the LogiCORE PCI interface in VHDL causes some back-end signals to
go unknown
Problem Description:
Urgency: Standard
General Description:
Trying to simulate the LogiCORE PCI interface in VHDL causes following outputs of the core
to the back-end module to go unknown.
s_data, m_data, dr_bus, i_idle, m_addr_n, idle, b_busy, backoff
Solution 1:
This is occurring due to the fact that the above mentioned signals have been declared as
INOUT in the PCI interface even though they are outputs. This problem is apparent only in
VHDL. The Verilog version does not have this problem.
The workaround is to change the declaration to OUT.
This will be fixed in the next release.
End of Record #7779 - Last Modified: 09/29/99 09:58 |
