Answers Database
2.1i COREGEN USER GUIDE: Errata sheet
Record #7784
Product Family: Software
Product Line: Coregen
Product Part: Coregen User Guide
Problem Title:
2.1i COREGEN USER GUIDE: Errata sheet
Problem Description:
Urgency: standard
General Description:
Errata listing for the 2.1i CORE Generator User Guide
Solution 1:
V2.1i CORE Generator User Guide Errata
Setup
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(Xilinx Solution #6693) - V2.1i COREGEN USER GUIDE: Permissions for $XILINX/coregen/ip
directory do not need to be 777
Design Flows
------------------------
Verilog behavioral simulation flow
(Xilinx Solution #6831) - V2.1i COREGEN USER GUIDE, VERILOG: "Error! Module name
previously declared" / Verilog parent design example contains redundant module declaration
(Xilinx Solution #6596) - V2.1i COREGEN, MTI, VERILOG: "WARNING[xx]:
.../XilinxCoreLib/xxxx.v(xx): Redefinition of macro: true" (or TRUE, false, or FALSE) when
analyzing/compiling COREGEN Verilog behavioral models
VHDL behavioral simulation flow
(Xilinx Solution #6861) - V2.1i COREGEN USER GUIDE, MTI, VHDL flow: 'Error
xxxmyadder8.vhd(20): near "myadder8_top" expecting COMPONENT' in VHDL
testbench example
End of Record #7784 - Last Modified: 09/28/99 17:39 |
