Answers Database
Virtex CLKDLL: 2 CLKDLLs cascaded together could cause the second CLKDLL's outputs invalid
Record #7816
Product Family: Hardware
Product Line: Virtex
Product Part: Virtex General Hardware
Problem Title:
Virtex CLKDLL: 2 CLKDLLs cascaded together could cause the second CLKDLL's outputs invalid
Problem Description:
Urgency: Hot
Problem description:
When cascading 2 CLKDLLs together with the Lock signal of the first CLKDLL
driving the RST of the second CLKDLL, the second CLKDLL never locks, and
its outputs don't have the correct clock frequencies. This problem happens on
the board after the design is downloaded. The functional or timing simulation
do not show this problem.
Solution 1:
The workaround is to insert a SRL16 and an inverter between the
LOCKED and RST pin of the first and second CLKDLL.
Please see the updated version of xapp132
http://support.xilinx.com/xapp/xapp132.pdf
End of Record #7816 - Last Modified: 01/20/00 16:18 |
