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How to infer SRL16 for Virtex/E devices in HDL (Verilog/VHDL)? (in EXEMPLAR and SYNPLIFY)
Record #7822
Product Family: Software
Product Line: Exemplar
Product Part: Leonardo Spectrum
Problem Title:
How to infer SRL16 for Virtex/E devices in HDL (Verilog/VHDL)? (in EXEMPLAR and SYNPLIFY)
Problem Description:
Urgency : Standard
General Description:
The latest version of Leonardo Specturm (currently 1999.1e) supports infering SRL16 for Virtex desig
n.
There are two variables to set:
(1) This variable enables SRL mapping (default false)
set virtex_map_srl true
(2) This variable packs SRL into a single slice (default false).
set virtex_map_srl_pack true
In Synplify, the SRL is mapped by default when possible.
Below is the coding style that will work for both EXEMPLAR and SYNPLIFY:
Solution 1:
-- VHDL example design of SRL16 inference for Virtex
-- This design infer 16 SRL16 with 16 pipeline delay
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity pipeline_delay is
generic (cycle : integer := 16;
width :integer := 16);
port (input :in std_logic_vector(width - 1 downto 0);
clk :in std_logic;
output :out std_logic_vector(width - 1 downto 0));
attribute clock_node :boolean;
attribute clock_node of clk : signal is TRUE;
end pipeline_delay;
architecture behav of pipeline_delay is
type my_type is array (0 to cycle -1) of
std_logic_vector(width -1 downto 0);
signal int_sig :my_type;
begin
main :process (clk)
begin
if clk'event and clk = '1' then
int_sig <= input & int_sig(0 to cycle - 2);
end if;
end process main;
output <= int_sig(cycle -1);
end behav;
Solution 2:
// Verilog Example SRL
//This design infer 3 SRL16 with 4 pipeline delay
module srle_example (clk, enable, data_in, result);
parameter cycle=4;
parameter width = 3;
input clk, enable;
input [0:width] data_in;
output [0:width] result;
reg [0:width-1] shift [cycle-1:0];
integer i;
always @(posedge clk)
begin
if (enable == 1) begin
for (i = (cycle-1);i >0; i=i-1) shift[i] =
shift[i-1];
shift[0] = data_in;
end
end
assign result = shift[cycle-1];
endmodule
End of Record #7822 - Last Modified: 12/02/99 10:31 |
