Answers Database 2.1i 4000XL Map/Fplan - Constrain from placement gets tripped up by Map route-thru. Record #7854 Product Family: Software Product Line: FPGA Implementation Product Part: map Product Version: 2.1i Problem Title: 2.1i 4000XL Map/Fplan - Constrain from placement gets tripped up by Map route-thru. Problem Description: Urgency: Standard General Description: A case has been seen where a floor plan constraints generated by a "Constrain from placement" operation are tripped up by a Cout to Fmap input connection where Map has   inserted a route-thru. The route-thru results in the physical design containing two net names that do not exist in the logical design. A "replace all with placement" floorplan operation results in a .mfp file containing floorplan constraints with the new net names:    fifo1/BU26_CINt    fifo1/BU53_CINt When the design is re-mapped with the floorplan constraints, most of the RLOCs from the Coregen macro are thrown away, except those that coincide with the invalid floorplan constraints. The result is a small macro involving just the logic that was not successfully floorplanned. If there is a carry chain involved that is only partially covered by this macro, PAR fails during placement because of the broken carry chain: ERROR:Place:562 - RPM "fifo1/hset" contains a partial carry logic chain. This     is not supported in the current release. Carry logic chains must either be     fully contained in the RPM or not in an RPM at all. The carry logic chain is     broken at CLB "fifo1/BU53_CINt" and is driven by CLB "fifo1/N133" which is     not contained in this RPM.     Please fix this problem before continuing. Solution 1: This problem is scheduled to be fixed in the next (as yet unnamed) release following version 2.1i. This release is currently scheduled for March, 2000. End of Record #7854 - Last Modified: 12/20/99 15:35

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