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Viewlogic VHDL simulation:How to simulate Xilinx Virtex primitives (e.g. ramb4_s4)
Record #7856
Product Family: Software
Product Line: ViewLogic
Product Part: Workview Office
Product Version: 7.5
Problem Title:
Viewlogic VHDL simulation:How to simulate Xilinx Virtex primitives (e.g. ramb4_s4)
Problem Description:
Urgency: Normal
Problem Description:
When customer is simulating in Viewlogic, the Xilinx primitives such as ramb4_s4 will not simulate.
Solution 1:
For functional simulation, you want to use the UNISIM and not the SIMPRIM
library. Under vhdl\src\unisims, you want to compile the following files in order:
unisim_vpkg.vhd
unisim_vcomp.vhd
unisim_vital.vhd
This will allow to simulate instantiated components in your code like a
RAMB4_S4_S4.
For timing simulation, Xilinx distributes a VHDL library for the RAMB4_S4_S4 that you have to comp
ile in SpeedWave before you compile the model containing the instance of the primitive. When you ge
t into Fusion, open the Library Manager and create a library SIMPRIM. From your Xilinx install dire
ctory (xilinx), add the file xilinx\vhdl\src\simprims\simprim_Vpackage.vhd and analyze. Then, in yo
ur user library, add xilinx\vhdl\src\simprims\simprim_VITAL.vhd and analyze. Then add and analyze y
our file that instantiates the RAMB4_S4_S4, e.g.
End of Record #7856 - Last Modified: 11/11/99 16:11 |
